ArchES Full-Duplex LVDS Interface

The Arches Full-Duplex LVDS Interface is a 10 Gbps to 40 Gbps LVDS Transceiver for Xilinx Virtex-5TM and Virtex-6TM FPGAs, providing designers with a flexible, easy-to-use method of connecting two FPGAs using a high-speed parallel LVDS bus. Industry-standard link speeds of 10Gbps and 40Gbps can be sustained using minimal I/O resources:

• 10Gbps full-duplex using one I/O bank in each direction
• 40Gbps full-duplex using four I/O banks in each direction

The core includes circuitry for clock forwarding, detection and recovery, serialization and de-serialization of parallel data, automatic training and alignment of data busses, flow control, clock domain crossing, as well as automatic link renegotiation if a link partner is reset, reprogrammed or hot-swapped. Users are presented with an abstracted low-latency synchronous FIFO interface of configurable width to exchange data with link partners. The design can be instantiated within an ISE design as a macro or as part of an EDK system as a PCORE.

Please see our LVDS full product feature sheet or contact us for more information.